An erase test is generally performed in an erase unit, e.g., a sector unit in an erase test for a semiconductor memory device. For example, an erase pulse may be impressed to a memory cell group divided into a plurality of groups until a group determined to have been subjected to the completion of erasure appears in performing a first erase test. Next, a second erase test may be performed on the memory cell group on the basis of the number of erase pulses at the detection of each group determined as having been subjected to the completion of erasure (as in, for example, Japanese Unexamined Patent Application Publication No. 2013-1378445).
However, when performing the erase test with division into the plurality of groups, the address of a firstly failed cell is stored, and a predetermined voltage for erasure is applied only when a fail has been determined as to each cell in the plural groups. In an address sequencer, the erase test is performed again in an overlapping form after having returned to the stored address. That is, the erase test is continued without application of the predetermined voltage, even if the fail has been determined with respect to the cell in one group is failed, and it is possible to reduce the influence of the failed cell. In the address sequencer, however, the erase test is performed again after having returned to the stored address, and therefore a loop of addresses has occurred and dispersion has arisen at testing time.